Advanced Printed Circuit Design
Mentor Graphics Hyperlynx for Signal Integrity Analysis.
Addressing Signal Integrity issues early in the design cycle will eliminate costly overdesign & re-spins.
Increasingly fast edge rates cause detrimental high-speed effects, even in PCB designs running at
low operating frequencies.
Pre Layout to create design strategies, PCB stackups, constraint routing, clock optimisation,
critical signal topologies and termination selection.
Post Layout allows Signal Integrity Analysis at three important stages, following part placement,
after critical net routing and after detailed routing of an entire board.